Title:

ASIC Design Engineer / Wireless Design Engineer

Location:

Edinburgh

Salary:

GBP 40,000 to GBP 50,000 per year (GBP Neg)

Description:

As a Senior Design Engineer you will be responsible for designing and implementing FPGA/ASIC based IP targeted towardscurrent and next generation wireless communications. Areas of interest to include Wireless systems physical layer(ideally 3G) and Communications systems from a physical layer perspective. Candidates will require a minimum of 5 yearsexperience and an understanding of DSP algorithm design through RTL is required.